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Features
* Single-voltage Operation * * *
- 5V Read - 5V Programming Fast Read Access Time - 70 ns Internal Erase/Program Control Sector Architecture - One 8K Word (16K Bytes) Boot Block with Programming Lockout - Two 4K Word (8K Bytes) Parameter Blocks - One 240K Word (480K Bytes) Main Memory Array Block Fast Sector Erase Time - 10 Seconds Byte-by-byte or Word-by-word Programming - 10 s Typical Hardware Data Protection Data Polling for End of Program Detection Low Power Dissipation - 50 mA Active Current - 100 A CMOS Standby Current Typical 10,000 Write Cycles
* * * * * *
4-megabit (512K x 8/ 256K x 16) Flash Memory AT49F4096A
Description
The AT49F4096A is a 5-volt, 4-megabit Flash memory organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When deselected, the CMOS standby current is less than 100 A. The device contains a user-enabled "boot block" protection feature. The AT49F4096A locates the boot block at lowest order addresses ("bottom boot"). To allow for simple in-system reprogrammability, the AT49F4096A does not require high-input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49F4096A is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis.
Pin Configurations
Pin Name A0 - A17 CE OE WE RESET I/O0 - I/O15 I/O15(A-1) BYTE NC Function Addresses Chip Enable Output Enable Write Enable Reset Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect
Rev. 1604D-FLASH-01/02
1
AT49F4096A SOIC (SOP)
AT49F4096A TSOP Top View Type 1
NC NC A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC NC NC A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE GND I/O15 / A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
AT49F4096A CBGA 7 x 7 mm Top View (Ball Down)
AT49F4096A CBGA 6 x 8 mm Top View (Ball Down)
1 A
A3 A7 RDY/BUSY WE A17 A6 A5 I/O0 I/O8 I/O9 I/O1 NC NC NC I/O2 I/O10 I/O11 I/O3 RESET VPP NC I/O5 I/O12 VCC I/O4 A9 A8 A10 A11 I/O7 I/O14 I/O13 I/O6 A13 A12 A14 A15 A16 BYTE I/O15 /A-1 VSS
1 A
2
3
4
5
6
7
8
2
3
4
5
6
A13 A11 B C A15 A12 D E
A8 VPP NC
NC
A7 A5 A3
A4 A2 A1 A0
B
A4
A14 A10 WE RST NC A17 A9 NC NC A6
C
A2
D
A1
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE F
E
A0
BYTE I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
F
CE
G
OE
H
VSS
Note:
"*" denotes a white dot on the package.
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AT49F4096A
The device is erased by executing the Erase command sequence; the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections, the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles. The 8K word boot block section includes a reprogramming lockout feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 5.5 volts or less are used. The boot sector is designed to contain user secure code. For the AT49F4096A, the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic "1" or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic "0", the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
AT49F4096A Block Diagram
VCC
GND OE WE CE RESET ADDRESS INPUTS
DATA INPUTS/OUTPUTS I/O0 - I/O15
CONTROL LOGIC
INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING MAIN MEMORY (240K WORDS) PARAMETER BLOCK 2 4K WORDS PARAMETER BLOCK 1 4K WORDS BOOT BLOCK 8K WORDS
Y DECODER X DECODER
3FFFF 04000 03FFF 03000 02FFF 02000 01FFF 00000
Device Operation
READ: The AT49F4096A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. 3
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RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if the boot block program lockout feature has been enabled (see "Boot Block Programming Lockout Override" section). ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased state of memory bits is a logic "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the boot block lockout has been enabled, the chip erase will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four sectors that can be individually erased. There are two 4K word parameter block sections, one boot block, and the main memory array block. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. Whenever the main memory block is erased and reprogrammed, the two parameter blocks should be erased and reprogrammed before the main memory block is erased again. Whenever a parameter block is erased and reprogrammed, the other parameter block should be erased and reprogrammed before the first parameter block is erased again. Whenever the boot block is erased and reprogrammed, the main memory block and the parameter blocks should be erased and reprogrammed before the boot block is erased again. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logic "0") on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The Data Polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write-protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH.
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Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections), a read from the following address location will show if programming the boot block is locked out - 00002H. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts during the entire chip erase, sector erase or word programming operation. When the RESET pin is brought back to TTL levels, the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see "Operating Modes" (for hardware operation) or "Software Product Identification Entry/Exit" on page 13. The manufacturer and device codes are the same for both modes. DATA POLLING: The AT49F4096A features Data Polling to indicate the end of a program cycle. During a program cycle, an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. TOGGLE BIT: In addition to Data Polling, the AT49F4096A provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F4096A in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) V CC power-on delay: once VCC has reached the V CC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
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Command Definition (in Hex)(1)
Command Sequence Read Chip Erase Sector Erase Byte/Word Program Boot Block Lockout(2) Product ID Entry Product ID Exit Product ID Exit Notes:
(3) (3)
Bus Cycles 1 6 6 4 6 3 3 1
1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 5555 xxxx Data DOUT AA AA AA AA AA AA F0
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
2AAA 2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55 55
5555 5555 5555 5555 5555 5555
80 80 A0 80 90 F0
5555 5555 Addr 5555
AA AA DIN AA
2AAA 2AAA
55 55
5555 SA
(4)
10 30
2AAA
55
5555
40
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex); A-1 and A15 - A17 (Don't Care). 1. The boot sector has the address range 00000H to 01FFFH. 2. Either one of the Product ID Exit commands can be used. 3. SA = sector addresses: (A17 - A0) SA = 01XXX for BOOT BLOCK SA = 02XXX for PARAMETER BLOCK 1 SA = 03XXX for PARAMETER BLOCK 2 SA = 3FXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on RESET with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC and AC Operating Range
AT49F4096A-70 Com. Operating Temperature (Case) Ind. VCC Power Supply -40C - 85C 5V 10% -40C - 85C 5V 10% 0C - 70C AT49F4096A-90 0C - 70C
Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X
OE VIL VIH X(1) X VIL VIH X
WE VIH VIL X VIH X X X
RESET VIH VIH VIH VIH VIH VIH VIL
Ai Ai Ai X
I/O DOUT DIN High-Z
Standby/Program Inhibit Program Inhibit
X Output Disable Reset Product Identification X X
High-Z X High-Z
Hardware
VIL
VIL
VIH
VIH
A1 - A17 = VIL, A9 = VH(3) A0 = VIL A1 - A17 = VIL, A9 = VH(3) A0 = VIH A0 = VIL, A1 - A17 = VIL A0 = VIH, A1 - A17 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
VIH
Notes:
1. 4. 5. 6.
X can be VIL or VIH. Refer to AC programming waveforms. VH = 12.0V 0.5V. Manufacturer Code: 161FH Device Code: 1692H 7. See details under "Software Product Identification Entry/Exit" on page 13.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Min Max 10.0 10.0 100.0 3.0 50.0 0.8 Units A A A mA mA V V V V
Note:
In the erase mode, ICC is 90 mA.
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AC Read Characteristics
AT49F4096A-70 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH tRO Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first RESET to Output Delay 0 0 0 800 Min Max 70 70 35 25 0 0 0 800 AT49F4096A-90 Min Max 90 90 40 25 Units ns ns ns ns ns ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID
CE t OE CE t OE t DF t t ACC t RO OUTPUT VALID OH
RESET OUTPUT
HIGH Z
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
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AT49F4096A
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Input Test Waveforms and Measurement Level
3.0V
0.0V
tR, tF < 5 ns
Output Test Load
70 ns 5.0V 90 ns 5.0V
30
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
This parameter is characterized and is not 100% tested.
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AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 50 50 0 40 Max Units ns ns ns ns ns ns ns ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte/Word Programming Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 50 40 5 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
PROGRAM CYCLE OE
CE t WP WE t WPH t BP
t AS
A0-A17
t AH 5555 t DS
t DH 2AAA 5555 ADDRESS 5555
DATA
AA
55
A0
INPUT DATA
AA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE t WP WE t AS t AH 5555 t DS DATA AA WORD 0 55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 Note 3 WORD 5 t DH 2AAA 5555 5555 2AAA Note 2 t EC t WPH
A0-A17
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
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Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 4. See tOE spec in "AC Read Characteristics" on page 8.
0
ns
Data Polling Waveforms
WE CE OE tDH I/O7 A0-A17 tOEH tOE An HIGH-Z tWR
An
An
An
An
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 5. See tOE spec in "AC Read Characteristics" on page 8.
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Toggle Bit Waveforms(1)(2)(3)
WE CE tOEH OE tDH I/O6 tOE HIGH-Z tWR tOEHP
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555
Boot Block Lockout Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 90 TO ADDRESS 5555
LOAD DATA 80 TO ADDRESS 5555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 5555
Software Product Identification Exit
LOAD DATA AA TO ADDRESS 5555 OR LOAD DATA F0 TO ANY ADDRESS
(1)(6)
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 40 TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
EXIT PRODUCT IDENTIFICATION MODE(4) PAUSE 1 second(2)
LOAD DATA F0 TO ADDRESS 5555
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).
Address Format: A15 - A0 (Hex); A-1 and A15 - A17 (Don't Care). 2. Boot Block Lockout feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).
Address Format: A15 - A0 (Hex); A-1 and A15 - A17 (Don't Care). A1 - A17 = VIL. Manufacturer Code is read for A0 = VIL. Device Code is read for A0 = VIH. The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturer Code: 161FH Device Code: 1692H Either one of the Product ID Exit commands can be used.
2.
3. 4. 5. 6.
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Ordering Information
tACC (ns) 70 ICC (mA) Active 50 Standby 0.3 Ordering Code AT49F4096A-70CC AT49F4096A-70CC AT49F4096A-70RC AT49F4096A-70TC AT49F4096A-70CI AT49F4096A-70CI AT49F4096A-70RI AT49F4096A-70TI 90 50 0.3 AT49F4096A-90CC AT49F4096A-90CC AT49F4096A-90RC AT49F4096A-90TC AT49F4096A-90CI AT49F4096A-90CI AT49F4096A-90RI AT49F4096A-90TI Package 48C1 48C5 44R 48T 48C1 48C5 44R 48T 48C1 48C5 44R 48T 48C1 48C5 44R 48T Operation Range Commercial (0 to 70C)
Industrial (-40 to 85C)
Commercial (0 to 70C)
Industrial (-40 to 85C)
Package Type 48C1 48C5 44R 48T 48-ball, 7 x 7 mm, Chip-size Ball Grid Array Package (CBGA) 48-ball, 6 x 8 mm, Chip-size Ball Grid Array Package (CBGA) 44-lead, 0.525" Wide, Plastic Gull Wing Small Outline (SOIC) 48-lead, Plastic Thin Small Outline Package (TSOP)
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Packaging Information
48C1 - CBGA
Dimensions in Millimeters and (Inches). Controlling dimension: millimeters.
7.10(0.280) 6.90(0.272)
A1 ID
7.10(0.280) 6.90(0.272)
SIDE VIEW
TOP VIEW
0.15 (0.006)MIN 1.20(0.047) MAX
0.875 (0.034) REF 5.25 (0.207)
8 7 6 5 4 3 2 1
1.625 (0.064)REF
A B C
0.75 (0.0295) BSC NON-ACCUMULATIVE
3.75 (0.148)
D E F
0.75 (0.0295) BSC NON-ACCUMULATIVE
0.30 (0.012) DIA BALL TYP
BOTTOM VIEW
04/11/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48C1, 48-ball (8 x 6 Array) 0.75 mm Pitch, 7 x 7 x 1.2 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C1 REV. A
R
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48C5 - CBGA
Dimensions in Millimeters and (Inches). Controlling dimension: millimeters.
6.10 (0.240) 5.90 (0.232)
A1 ID
8.10 (0.319) 7.90 (0.311)
0.25 (0.010)MIN
TOP VIEW
1.20 (0.047) MAX
SIDE VIEW
1.00(0.039) REF
6
4.00(0.157)
5 4 3 2 1
1.20 (0.047) REF
A B C
0.80 (0.0315) BSC NON-ACCUMULATIVE
D E F G H
5.60 (0.220)
0.80 (0.0315) BSC NON-ACCUMULATIVE
0.40 (0.016) DIA BALL TYP
BOTTOM VIEW
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48C5, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6 x 8 x 1.2 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C5 REV. A
R
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AT49F4096A
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AT49F4096A
44R - SOIC
Dimensions in Millimeters and (Inches). Controlling dimension: Inches.
0.508(0.020) 0.356(0.014)
13.46(0.530) 13.21(0.520)
16.18(0.637) 15.82(0.623)
PIN 1
1.27(0.050) BSC
28.32(1.115) 28.07(1.105)
2.67(0.105) 2.41(0.095) 0.33(0.130) 1.27(0.050)
0 ~ 8
1.00(0.039) 0.60(0.024)
0.250(0.010) 0.100(0.004)
04/11/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44R, 44-lead (0.525" Body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 44R REV. A
R
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48T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 11.90 0.50 NOM - - 1.00 20.00 18.40 12.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 12.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 48T REV. B
R
18
AT49F4096A
1604D-FLASH-01/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel (R) is the registered trademark of Atmel. Other terms and product names may be trademarks of others.
Printed on recycled paper.
1604D-FLASH-01/02 /xM

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